(1) Field of the invention
The present invention relates to a semiconductor storage device and, more particularly, to an electrically erasable programmable read-only memory (hereinafter referred to as "EPROM").
(2) Description of the prior art
The prior art EPROM of the kind to which the present invention relates is, as shown in FIG. 1, composed of a memory cell array 1, a plurality of column lines D.sub.0 -D.sub.3, a plurality of row lines W.sub.0 -W.sub.3, a column decoder 2, a column selector 3, a row decoder 4, a column pull-up circuit 5, a row pull-up circuit 6, a write circuit 17 and a sense amplifier 10.
Specifically, the memory cell array 1 comprises a plurality of electrically erasable programmable memory cells M.sub.00 -M.sub.33 each having a floating gate arranged in a matrix form, that is, in a row and a column direction. The column lines D.sub.0 -D.sub.3 serve to connect the memory cells M.sub.00 -M.sub.33 in the column direction. The row lines W.sub.0 -W.sub.3 serve to connect the memory cells M.sub.00 -M.sub.33 in the row direction. The column decoder 2 is composed of NOR gates NOR.sub.0 -NOR.sub.3 having inputs of address signals a.sub.0 -a.sub.1, and transfer gates constituted by N-channel depletion type MOS field effect transistors (hereinafter referred to as "MOSFETs") DY.sub.0 -DY.sub.3 to each of the gates of which a write signal W is commonly applied. The column selector 3 is composed of N-channel MOSFETs YS.sub.0 -YS.sub.3 which are driven by the outputs Y.sub.0 -Y.sub.3 from the column decoder 2 and serve to select the column lines D.sub.0 -D.sub.3. The row decoder 4 is composed of NOR gates NOR.sub.4 -NOR.sub.7 having inputs of address signals a.sub.2 -a.sub.3, and transfer gates constituted by N-channel depletion type MOSFETs DX.sub.0 -DX.sub.3 to each of the gates of which a write signal W is commonly applied, and serve to select the row lines W.sub.0 -W.sub.3. The column pull-up circuit 5 is composed of inverters IY.sub.00 -IY.sub.30 and P-channel MOSFETs PY.sub.01 -PY.sub.31. The inverters IY.sub.00 -IY.sub.30 comprise P-channel MOSFETs PY.sub.01 -PY.sub.31 and N-channel MOSFETs NY.sub.00 - NY.sub.30 which are connected in series between a write voltage terminal V.sub.PP and ground, and their inputs are connected with the outputs Y.sub.0 -Y.sub.3 from the column decoder 2. The P-channel MOSFETs PY.sub.00 -PY.sub.30 are connected between the write voltage terminal V.sub.PP and the outputs Y.sub.0 -Y.sub.3 from the column decoder 2, and applied to their gate electrodes are the outputs from the inverters IY.sub.00 -IY.sub.30. The row pull-up circuit 6 is composed of inverters IX.sub.00 -IX.sub.30 and P-channel MOSFETs PX.sub.01 -PX.sub.31. The inverters IX.sub.00 -IX.sub.30 comprise P-channel MOSFETs PX.sub.00 -PX.sub.30 and N-channel MOSFETs NX.sub.00 -NX.sub.30 which are connected in series between the write voltage terminal V.sub.PP and the ground, and their inputs are connected with the row lines W.sub.0 -W.sub.3. The P-channel MOSFETs PX.sub.01 -PX.sub.31 are connected between the write voltage terminal V.sub.PP and the row lines W.sub.0 -W.sub.3, and applied to their gate electrodes are the outputs from the inverters IX.sub.00 -IX.sub.30. The write circuit 17 is constituted by an N-channel MOSFET NW.sub.10 which is connected between the write voltage terminal V.sub.PP and the column selector 3 and to the gate electrode of which a write data D.sub.1 is applied. The sense amplifier 10 serves to read the data stored in the memory cells M.sub.00 -M.sub.33.
The operation of the EPROM of FIG. 1 will be described below.
First, the write operation will be explained. With the write voltage terminal V.sub.PP set for a high voltage (e.g., 12.5 V) and the write signal W set for a low level (0 V), address signals corresponding to the memory cell in which a data is to be stored are applied. For example, if a.sub.0 =0, a.sub.1 =0, a.sub.2 =0, and a.sub.3 =0, in the column decoder 2, NOR.sub.0 is selected so that it produces a high level 5 V, whereas NOR.sub.1 to NOR.sub.3 are not selected so that they produce a low level 0 V. Now it is assumed that the threshold voltage (hereinafter referred to as "V.sub.T ") of each of the N-channel MOSFETs DY.sub.0 -DY.sub.3 is, for example, -3 V. Since the low level 0 V is applied to the gates of DY.sub.0 -DY.sub.3, the selected column decoder output Y.sub.0 is charged up to .vertline.V.sub.TD .vertline.=3 V through the N-channel MOSFET DY.sub.0 so that DY.sub.0 is in a cut off state. On the other hand, the non-selected column decoder outputs Y.sub.1 -Y.sub.3 become the low level 0 V through the MOSFETs DY.sub.1 -DY.sub.3. Then, if the logical threshold voltage of the inverters IY.sub.00 -IY.sub.30 in the column pull-up circuit 5 is set for the voltage lower than .vertline.V.sub.TD .vertline.=3 V, the output from the inverter IY.sub.00 becomes the low level 0 V. Therefore, the P-channel MOSFET PY.sub.01 turns on so that the selected column decoder output Y.sub.0 is pulled up to the high voltage V.sub.PP =12.5 V through the P-channel MOSFET PY.sub.01. On the other hand, the outputs from the inverters IY.sub.10 to IY.sub.30 are the high level 12.5 V so that the P-channel MOSFETs PY.sub.11 to PY.sub.31 turn off. Thus, the low level 0 V of the non-selected column decoder outputs Y.sub.1 to Y.sub.3 are not influenced. In this state, only the N-channel MOSFET YS.sub.0 constituting a part of the column selector 3 turns on so that the write circuit 17 is connected with the column line D.sub.0 through the MOSFET YS.sub.0. Further, the row decoder 4 and the row pull-up circuit 6, which have the same circuit arrangements as the column decoder 2 and the column pull-up circuit 5, respectively, select the row line W.sub.0 to be pulled up to the high voltage 12.5 V while the non-selected W.sub.1 to W.sub.3 are at the low level 0 V.
In this way, the memory cell M.sub.00 is selected. The selected memory cell M.sub.00 is connected with the write circuit 17 through the N-channel MOSFET YS.sub.0 in the column selector 3.
Now, if the write data D.sub.1 is the high level V.sub.PP =12.5 V, the N-channel MOSFET NW.sub.10 turns on so that the drain electrode of the memory cell M.sub.00 is connected with the write voltage terminal V.sub.pp through the N-channel MOSFET NW.sub.10 constituting the write circuit 17 and the N-channel MOSFET YS.sub.0 in the column selector 3. Thus, the threshold voltage V.sub.TM of the memory cell M.sub.00 is shifted from V.sub.TM =2 V to V.sub.TM =10 V. The load line obtained with the potential V.sub.D1 at the selected column and the current I.sub.D1 flowing through the MOSFET NW.sub.10 in the write circuit 17 and the MOSFET YS.sub.0 in the column selector 3 is shown in FIG. 3A. Since V.sub.PP =12.5 V is previously applied to the gates of the MOSFET NW.sub.10 and the MOSFET YS.sub.0, I.sub.D1 flows when V.sub.D1 &lt;(V.sub.PP -V.sub.TN) (V.sub.TN represents the threshold voltage of the MOSFET NW.sub.10 and the MOSFET YSo); the lower the voltage V.sub.D1, the larger the current I.sub.D1. In order to shift the threshold voltage V.sub.TM of the memory cell M.sub.00, the load line must be set at the upper right of a write starting point (represented by "." on the graph) given by V.sub.W and I.sub.w.
On the other hand, the write data D.sub.1 is the low level 0 V, the MOSFET NW.sub.10 in the write circuit 17 turns off so that no voltage is applied to the drain electrode of the selected memory cell. Thus, the selected memory cell M.sub.00 is in a non-writing state so that the V.sub.TM is not shifted but maintains e.g., V.sub.TM =2 V.
Next, the read operation will be explained. With the write voltage terminal V.sub.PP set for a power supply voltage V.sub.CC =5 V and the write signal W set for a high level (5 V), address signals corresponding to the memory cell from which a data is to be read out are applied. For example, if a.sub.0 =0, a.sub.1 =0, a.sub.2 =0, and a.sub.3 =0, in the column decoder 2, NOR.sub.0 is selected so that it produces a high level 5 V, whereas NOR.sub.1 to NOR.sub.3 are not selected so that they produce a low level 0 V. Since the high level 5 V has been applied to each of the gates of the MOSFET DY.sub.0 -DY.sub.3, the selected column decoder output Y.sub.0 is the high level, whereas the non-selected column decoder outputs Y.sub.1 -Y.sub.3 are the low level 0 V. In the column pull-up circuit 5, the output from the inverter IY.sub.00 becomes the low level 0 V so that the P-channel MOSFET PY.sub.01 turns on. Thus, the selected column decoder output Y.sub.0 is pulled up to the high level voltage V.sub.CC =5 V also through the MOSFET PY.sub.01. On the other hand, the outputs from the inverters IY.sub.10 to IY.sub.30 are the high level V.sub.CC =5 V so that the P-channel MOSFETs PY.sub.11 to PY.sub.31 turn off. Thus, the low level 0 V of the non-selected column decoder outputs Y.sub.1 to Y.sub.3 are not influenced. In this state, only the N-channel MOSFET YS.sub.0 in the column selector 3 turns on so that the input of the sense amplifier 10 is connected with the column line D.sub.0 through this N-channel MOSFET YS.sub.0. Further, the row decoder 4 and the row pull-up circuit 6, which have the same circuit arrangements as the column decoder 2 and the column pull-up circuit 5, respectively, select the row line W.sub.0 to be pulled up to the high level 5 V while the non-selected W.sub.1 to W.sub.3 are at the low level 0 V.
In this way, the memory cell M.sub.00 is selected. If the threshold voltage V.sub.TM of the selected memory cell M.sub.00 is V.sub.TM =2 V which has not been shifted, the memory cell M.sub.00 turns on so that the low level is produced from the sense amplifier 10. If V.sub.TM of the selected memory cell M.sub.00 is V.sub.TM =10 V shifted, the memory cell M.sub.00 does not turn on, but the high level is produced from the sense amplifier 10.
As readily understood from the description hitherto made, in an EPROM, it is possible to electrically store any data in any memory cell, and also possible to read the data stored in any memory cell.
FIG. 2 shows another conventional EPROM. In FIG. 2, like reference numerals and symbols refer to like parts in FIG. 1. It should be noted that the EPROM of FIG. 2 comprises a voltage boosting circuit 9 in addition to the components as shown in FIG. 1 and the write circuit 17 in FIG. 1 is modified as a write circuit 27.
Specifically, the voltage boosting circuit 9 is composed of N-channel MOSFETs NCP.sub.0 and NCP.sub.1 which are connected in series between the write voltage terminal V.sub.PP and an output terminal CP.sub.OUT of the voltage boosting circuit and the gate electrodes of which are connected with the corresponding drain electrodes; a capacitor element C one terminal of which is connected with the junction point of NCP.sub.0 and NCP.sub.1 and the other terminal of which a clock signal .phi. is applied to; and an N-channel depletion type MOSFET DCP.sub.0 the drain electrode of which is connected with a power supply voltage terminal V.sub.CC, the source electrode of which is connected with the output terminal CP.sub.OUT of the voltage boosting circuit 9 and the gate electrode of which the write signal W is applied to.
The write circuit 27 is composed of an N-channel depletion type MOSFET DW.sub.20 and an N-channel MOSFET NW.sub.20 connected in series between the write voltage terminal V.sub.PP and the column selector 3; a load element RW.sub.21 and an N-channel MOSFET NW.sub.21 connected in series between the output terminal CP.sub.OUT of the voltage boosting circuit 9 and the ground. The gate electrode of the MOSFET NW.sub.21 receives a signal obtained by inverting the write data D.sub.1 by an inverter IW.sub.20. The gate electrode of the MOSFET DW.sub.20 is connected with its source electrode and the gate electrode of the N-channel MOSFET NW.sub.20 is connected with the junction point of the load element RW.sub.21 and the N-channel MOSFET NW.sub.21. Further, it should be noted that the output terminal CP.sub.out of the voltage boosting circuit 9 is also connected with each of the source electrodes of the P-channel MOSFETs PY.sub.00 -PY.sub.30 constituting the inverters IY.sub.00 -IY.sub.30 and of the P-channel MOSFETs PY.sub.01 -PY.sub.31 all in the column pull-up circuit 5.
The write operation of the EPROM of FIG. 2 will be explained. With the write voltage terminal V.sub.pp set for the high voltage 12.5 V and the write signal W set for the low level 0 V, if the clock signal .phi. is applied to the voltage boosting circuit 9, the voltage V.sub.cp (e.g., V.sub.cp =20 V) boosted by the voltage boosting circuit 9 will be produced from its output terminal CP.sub.out. If the address signals of a.sub.0 =0, a.sub.1 =0, a.sub.2 =0 and a.sub.3 =0 are applied, as described in connection with FIG. 1, the decoder output Y.sub.0 is selected and then pulled up to .vertline.V.sub.TD .vertline.=3 V. Further, the output of the inverter IY.sub.00 in the column pull-up circuit 5 becomes the low level 0 V, so that the P-channel MOSFET PY.sub.01 turns on. Thus, the selected decoder output Y.sub.0 will be pulled up to the boosted voltage (V.sub.CP =20 V) produced from the output terminal CP.sub.OUT of the boosting circuit 9 through the P-channel MOSFET PY.sub.01. Accordingly, the boosted voltage V.sub.CP =20 V is applied to the gate electrode of the N-channel MOSFET YS.sub.0 so that it turns on. As a result, the column line D.sub.0 is connected with the write circuit 27.
Further, as described in connection with FIG. 1, the row decoder 4 and the row pull-up circuit 6 select the row line W.sub.0 to be pulled up to the high voltage V.sub.PP =12.5 V. In this way, the memory cell M.sub.00 in the memory cell array is selected.
Now, if the write data D.sub.1 is at a high level, the output from the inverter IW.sub.20 becomes a low level 0 V. Then, the N-channel MOSFET NW.sub.21 turns off, so that the potential at the junction point of the load element RW.sub.21 and the N-channel MOSFET NW.sub.21 connected in series between the terminal CP.sub.OUT and the ground becomes the boosted voltage V.sub.CP =20 V produced from the voltage boosting circuit 9. Thus, the boosted voltage V.sub.CP =20 V is applied to the gate electrode of the N-channel MOSFET NW.sub.20, so that NW.sub.20 turns on. Accordingly, the drain electrode of the memory cell M.sub.00 is connected with the write voltage terminal V.sub.PP through the N-channel MOSFET NW.sub.20 and the N-channel depletion type MOSFET DW.sub.20 in the write circuit 27 and the N-channel MOSFET YS.sub.0 in the column selector 3. As a result, the threshold voltage V.sub.TM of the memory cell M.sub.00 will be shifted e.g., from V.sub.TM =2 V to V.sub.TM =10 V.
Now, FIG. 3B shows the load line obtained with the potential V.sub.D1 of the selected column line and the current I.sub.D1 flowing through MOSFETs DW.sub.20 and NW.sub.20 in the write circuit 27 and the MOSFET YS.sub.0 in the column selector 3. Now it should be noted that the boosted voltage V.sub.CP =20 V is previously applied to the gate electrode of the N-channel MOSFET NW.sub.20 in the write circuit 27 and that of the N-channel MOSFET YS.sub.0 in the column selector 3. For this reason, if the threshold voltages V.sub.TN of the N-channel MOSFETs NW.sub.20 and YS.sub.0 are V.sub.TN =1 V, respectively, even if the V.sub.PP =12.5 V is applied to their source electrodes, they are not cut off. As a result, the load line is determined by the N-channel depletion type MOSFET DW.sub.20 and the current I.sub.D1 flows when 0.ltoreq.V.sub.D1 &lt;V.sub.PP. The current I.sub.D1 will be limited by I.sub.DW20 expressed by the following equation: ##EQU1##
In Equation (1), .beta..sub.DW20 and V.sub.TDW20 are .beta. and the threshold voltage of the N-channel MOSFET DW.sub.20, and the limit current I.sub.DW20 can be defined by setting .beta..sub.DW20 and V.sub.TDW20. In this case also, it should be noted that in order to shift the threshold voltage V.sub.TM of the memory cell, the load line must be set at the upper right of the write starting point (represented by ".") given by V.sub.W and I.sub.W.
On the other hand, if the write data D.sub.1 is the low level, the output from the inverter IW.sub.20 becomes the high level, so that the N-channel MOSFET NW.sub.21 turns on. Thus, the junction point of the load element RW.sub.21 and the MOSFET NW.sub.21 becomes the low level so that the MOSFET NW.sub.20 turns off. Then, no voltage is applied to the drain electrode of the selected memory cell M.sub.00 so that the memory cell M.sub.00 is in a non-writing state. Therefore, V.sub.TM thereof is not shifted but V.sub.TN =2 V is maintained. Additionally, in the read-out operation, the write voltage terminal V.sub.PP is set for the power supply voltage V.sub.CC =5 V and the write signal W is set for the high level V.sub.CC =5 V. In this case, the N-channel MOSFET DCP.sub.0 turns on so that the voltage of V.sub.CC =5 V is extracted from the output terminal CP.sub.OUT of the voltage boosting circuit 9. Therefore, the read operation can be executed in the same manner as in the EPROM shown in FIG. 1.
The prior art EPROMs described above have the following defects.
In the prior art EPROM shown in FIG. 1, as the load line of the write circuit 17 has the characteristic as shown in FIG. 3A, if the load line is so set that it starts from V.sub.PP -V.sub.TN and passes the upper right of the write starting point (represented by ".") in order to shift the threshold voltage V.sub.TM of the memory cell, the current I.sub.D1 in the range of V.sub.D1 &lt;V.sub.W becomes very large.
Also, as the current I.sub.D1 is supplied from the write voltage terminal V.sub.PP, if V.sub.D1 becomes low, the current (hereinafter referred to as "I.sub.PP ") flowing from the write voltage terminal V.sub.PP also becomes very large.
On the other hand, in the prior art EPROM shown in FIG. 2, the load line of the write circuit 27 has the characteristic as shown in FIG. 3B. As described above, I.sub.D1 is limited by I.sub.DW20 so that I.sub.PP does not become large. However, in the range of I.sub.D1 is small, that is, I.sub.D1 &lt;&lt;I.sub.W, V.sub.D1 becomes a high voltage which is substantially equal to V.sub.PP. Thus, the high voltage which is substantially equal to V.sub.PP will be applied to the drain electrode of a memory cell. Application of such a high voltage to the drain electrode of the memory cell may break the memory cell, or cause the data stored in the memory cell to disappear, thereby greatly deteriorating the reliability of the memory cell.
In this way, the setting I.sub.D1 and V.sub.D1 in an EPROM is a very important matter. Nevertheless, both the prior art EPROMs could not have these values set in a desired manner.